********** Mapped Logic ********** |
$OpTx$FX_DC$11 <= (accu_in(0) AND accu_in(1) AND accu_in(2) AND
$OpTx$FX_DC$7); |
$OpTx$FX_DC$12 <= (cnt(0) AND cnt(1) AND cnt(2) AND $OpTx$FX_DC$6); |
$OpTx$FX_DC$3 <= ((accu_in(0) AND EN_DISP(0) AND LED(1))
OR (accu_out(0) AND NOT EN_DISP(0) AND NOT LED(1)) OR (cnt(0) AND NOT EN_DISP(0) AND LED(1)) OR (accu_out(4) AND EN_DISP(0) AND NOT LED(1))); |
$OpTx$FX_DC$6 <= (NOT TASTER_U AND XLXN_204 AND LED(0) AND LED(1)); |
$OpTx$FX_DC$7 <= (NOT TASTER_U AND XLXN_204 AND NOT LED(0) AND LED(1)); |
$OpTx$FX_DC$9 <= (cnt(0) AND cnt(1) AND $OpTx$FX_DC$6); |
A <= ((NOT XLXN_307/XLXN_307_D2 AND d2/d2_D2 AND NOT $OpTx$FX_DC$3)
OR (NOT XLXN_307/XLXN_307_D2 AND d2/d2_D2 AND d3/d3_D2) OR (XLXN_307/XLXN_307_D2 AND NOT d2/d2_D2 AND $OpTx$FX_DC$3 AND d3/d3_D2) OR (NOT XLXN_307/XLXN_307_D2 AND NOT d2/d2_D2 AND $OpTx$FX_DC$3 AND NOT d3/d3_D2)); |
B <= ((XLXN_307/XLXN_307_D2 AND d2/d2_D2 AND NOT $OpTx$FX_DC$3)
OR (XLXN_307/XLXN_307_D2 AND d2/d2_D2 AND d3/d3_D2) OR (XLXN_307/XLXN_307_D2 AND $OpTx$FX_DC$3 AND d3/d3_D2) OR (d2/d2_D2 AND NOT $OpTx$FX_DC$3 AND d3/d3_D2) OR (NOT XLXN_307/XLXN_307_D2 AND d2/d2_D2 AND $OpTx$FX_DC$3 AND NOT d3/d3_D2)); |
C <= ((XLXN_307/XLXN_307_D2 AND d2/d2_D2 AND d3/d3_D2)
OR (d2/d2_D2 AND NOT $OpTx$FX_DC$3 AND d3/d3_D2) OR (XLXN_307/XLXN_307_D2 AND NOT d2/d2_D2 AND NOT $OpTx$FX_DC$3 AND NOT d3/d3_D2)); |
D <= ((XLXN_307/XLXN_307_D2 AND d2/d2_D2 AND $OpTx$FX_DC$3)
OR (XLXN_307/XLXN_307_D2 AND NOT d2/d2_D2 AND NOT $OpTx$FX_DC$3 AND d3/d3_D2) OR (NOT XLXN_307/XLXN_307_D2 AND d2/d2_D2 AND NOT $OpTx$FX_DC$3 AND NOT d3/d3_D2) OR (NOT XLXN_307/XLXN_307_D2 AND NOT d2/d2_D2 AND $OpTx$FX_DC$3 AND NOT d3/d3_D2)); |
E <= (($OpTx$FX_DC$3 AND NOT d3/d3_D2)
OR (NOT XLXN_307/XLXN_307_D2 AND d2/d2_D2 AND NOT d3/d3_D2) OR (NOT XLXN_307/XLXN_307_D2 AND NOT d2/d2_D2 AND $OpTx$FX_DC$3)); |
FTCPE_EN_DISP0: FTCPE port map (EN_DISP(0),'1',CLK_SLOW,NOT TASTER_RES,'0'); |
FDCPE_EN_DISP1: FDCPE port map (EN_DISP(1),EN_DISP(0),CLK_SLOW,'0',NOT TASTER_RES); |
F <= ((XLXN_307/XLXN_307_D2 AND NOT d2/d2_D2 AND NOT d3/d3_D2)
OR (XLXN_307/XLXN_307_D2 AND $OpTx$FX_DC$3 AND NOT d3/d3_D2) OR (NOT XLXN_307/XLXN_307_D2 AND d2/d2_D2 AND d3/d3_D2) OR (NOT d2/d2_D2 AND $OpTx$FX_DC$3 AND NOT d3/d3_D2)); |
G <= ((NOT XLXN_307/XLXN_307_D2 AND NOT d2/d2_D2 AND NOT d3/d3_D2)
OR (XLXN_307/XLXN_307_D2 AND d2/d2_D2 AND $OpTx$FX_DC$3 AND NOT d3/d3_D2)); |
FTCPE_LED0: FTCPE port map (LED(0),LED_T(0),CLK_SLOW,'0',NOT TASTER_RES);
LED_T(0) <= (NOT TASTER_R AND XLXN_163 AND NOT accu_in(5)/accu_in(5)_CE); |
FTCPE_LED1: FTCPE port map (LED(1),LED_T(1),CLK_SLOW,'0',NOT TASTER_RES);
LED_T(1) <= (NOT TASTER_R AND XLXN_163 AND NOT LED(0) AND LED(1)); |
XLXI_15/S7_4/X0/XLXI_15/S7_4/X0_D <= accu_in(4)
XOR XLXI_15/S7_4/X0/XLXI_15/S7_4/X0_D <= accu_out(4); |
XLXI_15/S7_4/X3/XLXI_15/S7_4/X3_D <= accu_in(7)
XOR XLXI_15/S7_4/X3/XLXI_15/S7_4/X3_D <= accu_out(7); |
XLXI_15/S7_4/XLXN_28/XLXI_15/S7_4/XLXN_28_D2 <= ((accu_in(4) AND accu_out(4))
OR (accu_out(3) AND XLXI_15/S7_4/X0/XLXI_15/S7_4/X0_D AND NOT XLXI_15/XLXI_1/X3/XLXI_15/XLXI_1/X3_D) OR (XLXI_15/S7_4/X0/XLXI_15/S7_4/X0_D AND XLXI_15/XLXI_1/X3/XLXI_15/XLXI_1/X3_D AND XLXI_15/XLXI_1/XLXN_27/XLXI_15/XLXI_1/XLXN_27_D2)); |
XLXI_15/S7_4/XLXN_34/XLXI_15/S7_4/XLXN_34_D2 <= ((accu_in(5) AND accu_out(5))
OR (accu_in(5) AND XLXI_15/S7_4/XLXN_28/XLXI_15/S7_4/XLXN_28_D2) OR (accu_out(5) AND XLXI_15/S7_4/XLXN_28/XLXI_15/S7_4/XLXN_28_D2)); |
XLXI_15/XLXI_1/X3/XLXI_15/XLXI_1/X3_D <= accu_in(3)
XOR XLXI_15/XLXI_1/X3/XLXI_15/XLXI_1/X3_D <= accu_out(3); |
XLXI_15/XLXI_1/XLXN_27/XLXI_15/XLXI_1/XLXN_27_D2 <= ((accu_in(2) AND accu_out(2))
OR (accu_in(2) AND XLXI_15/XLXI_1/XLXN_34/XLXI_15/XLXI_1/XLXN_34_D2) OR (accu_out(2) AND XLXI_15/XLXI_1/XLXN_34/XLXI_15/XLXI_1/XLXN_34_D2)); |
XLXI_15/XLXI_1/XLXN_34/XLXI_15/XLXI_1/XLXN_34_D2 <= ((accu_in(1) AND accu_out(1))
OR (accu_in(0) AND accu_in(1) AND accu_out(0)) OR (accu_in(0) AND accu_out(0) AND accu_out(1))); |
FDCPE_XLXN_163: FDCPE port map (XLXN_163,TASTER_R,CLK_SLOW,'0','0'); |
FDCPE_XLXN_204: FDCPE port map (XLXN_204,TASTER_U,CLK_SLOW,'0','0'); |
XLXN_307/XLXN_307_D2 <= ((accu_in(1) AND EN_DISP(0) AND LED(1))
OR (accu_out(1) AND NOT EN_DISP(0) AND NOT LED(1)) OR (cnt(1) AND NOT EN_DISP(0) AND LED(1)) OR (accu_out(5) AND EN_DISP(0) AND NOT LED(1))); |
FDCPE_accu_in0: FDCPE port map (accu_in(0),accu_in_D(0),CLK_SLOW,NOT TASTER_RES,'0');
accu_in_D(0) <= ((NOT accu_in(0) AND $OpTx$FX_DC$7) OR (accu_in(0) AND NOT accu_in(5)/accu_in(5)_CE AND NOT $OpTx$FX_DC$7)); |
FTCPE_accu_in1: FTCPE port map (accu_in(1),accu_in_T(1),CLK_SLOW,NOT TASTER_RES,'0');
accu_in_T(1) <= ((accu_in(0) AND NOT accu_in(1) AND accu_in(5)/accu_in(5)_CE) OR (accu_in(0) AND NOT accu_in(5)/accu_in(5)_CE AND $OpTx$FX_DC$7) OR (NOT accu_in(0) AND accu_in(1) AND accu_in(5)/accu_in(5)_CE AND NOT $OpTx$FX_DC$7)); |
FTCPE_accu_in2: FTCPE port map (accu_in(2),accu_in_T(2),CLK_SLOW,NOT TASTER_RES,'0');
accu_in_T(2) <= ((accu_in(1) AND NOT accu_in(2) AND accu_in(5)/accu_in(5)_CE) OR (NOT accu_in(1) AND accu_in(2) AND accu_in(5)/accu_in(5)_CE) OR (accu_in(0) AND accu_in(1) AND NOT accu_in(5)/accu_in(5)_CE AND $OpTx$FX_DC$7)); |
FDCPE_accu_in3: FDCPE port map (accu_in(3),accu_in_D(3),CLK_SLOW,NOT TASTER_RES,'0');
accu_in_D(3) <= ((accu_in(2) AND accu_in(5)/accu_in(5)_CE) OR (NOT accu_in(3) AND $OpTx$FX_DC$11) OR (accu_in(3) AND NOT accu_in(5)/accu_in(5)_CE AND NOT $OpTx$FX_DC$11)); |
FDCPE_accu_in4: FDCPE port map (accu_in(4),accu_in(3),CLK_SLOW,NOT TASTER_RES,'0',accu_in_CE(4));
accu_in_CE(4) <= (NOT TASTER_R AND XLXN_163 AND NOT LED(1)); |
accu_in(5)/accu_in(5)_CE <= (NOT TASTER_R AND XLXN_163 AND NOT LED(1)); |
FDCPE_accu_in5: FDCPE port map (accu_in(5),accu_in(4),CLK_SLOW,NOT TASTER_RES,'0',accu_in_CE(5));
accu_in_CE(5) <= (NOT TASTER_R AND XLXN_163 AND NOT LED(1)); |
FDCPE_accu_in6: FDCPE port map (accu_in(6),accu_in(5),CLK_SLOW,NOT TASTER_RES,'0',accu_in_CE(6));
accu_in_CE(6) <= (NOT TASTER_R AND XLXN_163 AND NOT LED(1)); |
FDCPE_accu_in7: FDCPE port map (accu_in(7),accu_in(6),CLK_SLOW,NOT TASTER_RES,'0',accu_in_CE(7));
accu_in_CE(7) <= (NOT TASTER_R AND XLXN_163 AND NOT LED(1)); |
FTCPE_accu_out0: FTCPE port map (accu_out(0),accu_in(0),CLK_SLOW,NOT TASTER_RES,'0',accu_out_CE(0));
accu_out_CE(0) <= (cnt(0) AND accu_in(5)/accu_in(5)_CE); |
FDCPE_accu_out1: FDCPE port map (accu_out(1),accu_out_D(1),CLK_SLOW,NOT TASTER_RES,'0',accu_out_CE(1));
accu_out_D(1) <= (accu_in(0) AND accu_out(0)) XOR accu_out_D(1) <= ((accu_in(1) AND NOT accu_out(1)) OR (NOT accu_in(1) AND accu_out(1))); accu_out_CE(1) <= (cnt(0) AND accu_in(5)/accu_in(5)_CE); |
FTCPE_accu_out2: FTCPE port map (accu_out(2),accu_out_T(2),CLK_SLOW,NOT TASTER_RES,'0',accu_out_CE(2));
accu_out_T(2) <= ((accu_in(2) AND XLXI_15/XLXI_1/XLXN_34/XLXI_15/XLXI_1/XLXN_34_D2) OR (NOT accu_in(2) AND NOT XLXI_15/XLXI_1/XLXN_34/XLXI_15/XLXI_1/XLXN_34_D2)); accu_out_CE(2) <= (cnt(0) AND accu_in(5)/accu_in(5)_CE); |
FDCPE_accu_out3: FDCPE port map (accu_out(3),accu_out_D(3),CLK_SLOW,NOT TASTER_RES,'0',accu_out_CE(3));
accu_out_D(3) <= XLXI_15/XLXI_1/X3/XLXI_15/XLXI_1/X3_D XOR accu_out_D(3) <= XLXI_15/XLXI_1/XLXN_27/XLXI_15/XLXI_1/XLXN_27_D2; accu_out_CE(3) <= (cnt(0) AND accu_in(5)/accu_in(5)_CE); |
FDCPE_accu_out4: FDCPE port map (accu_out(4),accu_out_D(4),CLK_SLOW,NOT TASTER_RES,'0',accu_out_CE(4));
accu_out_D(4) <= XLXI_15/S7_4/X0/XLXI_15/S7_4/X0_D XOR accu_out_D(4) <= ((NOT accu_out(3) AND NOT XLXI_15/XLXI_1/X3/XLXI_15/XLXI_1/X3_D) OR (XLXI_15/XLXI_1/X3/XLXI_15/XLXI_1/X3_D AND NOT XLXI_15/XLXI_1/XLXN_27/XLXI_15/XLXI_1/XLXN_27_D2)); accu_out_CE(4) <= (cnt(0) AND accu_in(5)/accu_in(5)_CE); |
FTCPE_accu_out5: FTCPE port map (accu_out(5),accu_out_T(5),CLK_SLOW,NOT TASTER_RES,'0',accu_out_CE(5));
accu_out_T(5) <= ((accu_in(5) AND XLXI_15/S7_4/XLXN_28/XLXI_15/S7_4/XLXN_28_D2) OR (NOT accu_in(5) AND NOT XLXI_15/S7_4/XLXN_28/XLXI_15/S7_4/XLXN_28_D2)); accu_out_CE(5) <= (cnt(0) AND accu_in(5)/accu_in(5)_CE); |
FTCPE_accu_out6: FTCPE port map (accu_out(6),accu_out_T(6),CLK_SLOW,NOT TASTER_RES,'0',accu_out_CE(6));
accu_out_T(6) <= ((accu_in(6) AND XLXI_15/S7_4/XLXN_34/XLXI_15/S7_4/XLXN_34_D2) OR (NOT accu_in(6) AND NOT XLXI_15/S7_4/XLXN_34/XLXI_15/S7_4/XLXN_34_D2)); accu_out_CE(6) <= (cnt(0) AND accu_in(5)/accu_in(5)_CE); |
FDCPE_accu_out7: FDCPE port map (accu_out(7),accu_out_D(7),CLK_SLOW,NOT TASTER_RES,'0',accu_out_CE(7));
accu_out_D(7) <= XLXI_15/S7_4/X3/XLXI_15/S7_4/X3_D XOR accu_out_D(7) <= ((EXP6_.EXP) OR (accu_in(6) AND XLXI_15/S7_4/XLXN_34/XLXI_15/S7_4/XLXN_34_D2) OR (accu_out(6) AND XLXI_15/S7_4/XLXN_34/XLXI_15/S7_4/XLXN_34_D2)); accu_out_CE(7) <= (cnt(0) AND accu_in(5)/accu_in(5)_CE); |
FDCPE_cnt0: FDCPE port map (cnt(0),cnt_D(0),CLK_SLOW,NOT TASTER_RES,'0');
cnt_D(0) <= ((NOT cnt(0) AND $OpTx$FX_DC$6) OR (cnt(1) AND accu_in(5)/accu_in(5)_CE) OR (cnt(0) AND NOT accu_in(5)/accu_in(5)_CE AND NOT $OpTx$FX_DC$6)); |
FDCPE_cnt1: FDCPE port map (cnt(1),cnt_D(1),CLK_SLOW,NOT TASTER_RES,'0');
cnt_D(1) <= ((cnt(2) AND accu_in(5)/accu_in(5)_CE) OR (cnt(1) AND NOT accu_in(5)/accu_in(5)_CE AND NOT $OpTx$FX_DC$9) OR (cnt(0) AND NOT cnt(1) AND LED(1) AND accu_in(5)/accu_in(5)_CE) OR (cnt(0) AND NOT cnt(1) AND LED(1) AND $OpTx$FX_DC$6)); |
FDCPE_cnt2: FDCPE port map (cnt(2),cnt_D(2),CLK_SLOW,NOT TASTER_RES,'0');
cnt_D(2) <= ((NOT cnt(2) AND $OpTx$FX_DC$9) OR (cnt(3) AND accu_in(5)/accu_in(5)_CE) OR (cnt(2) AND NOT accu_in(5)/accu_in(5)_CE AND NOT $OpTx$FX_DC$9)); |
FDCPE_cnt3: FDCPE port map (cnt(3),cnt_D(3),CLK_SLOW,NOT TASTER_RES,'0');
cnt_D(3) <= ((NOT cnt(3) AND $OpTx$FX_DC$12) OR (cnt(3) AND NOT accu_in(5)/accu_in(5)_CE AND NOT $OpTx$FX_DC$12)); |
d2/d2_D2 <= ((accu_in(2) AND EN_DISP(0) AND LED(1))
OR (accu_out(2) AND NOT EN_DISP(0) AND NOT LED(1)) OR (cnt(2) AND NOT EN_DISP(0) AND LED(1)) OR (accu_out(6) AND EN_DISP(0) AND NOT LED(1))); |
d3/d3_D2 <= ((accu_in(3) AND EN_DISP(0) AND LED(1))
OR (accu_out(3) AND NOT EN_DISP(0) AND NOT LED(1)) OR (cnt(3) AND NOT EN_DISP(0) AND LED(1)) OR (accu_out(7) AND EN_DISP(0) AND NOT LED(1))); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |