Equations

********** Mapped Logic **********
$OpTx$FX_DC$111 <= (NOT note(1)/note(1)_D2 AND NOT note(0)/note(0)_D2 AND
      note(2)/note(2)_D2);
$OpTx$FX_DC$116 <= ((song_ind_0__or0000/song_ind_0__or0000_D2 AND
      song_ind_or0000/song_ind_or0000_D2)
      OR (song_ind(2) AND song_ind(3) AND song_ind(4) AND
      song_ind_0__or0000/song_ind_0__or0000_D2 AND
      song_ind_Madd__add0000__and0000/song_ind_Madd__add0000__and0000_D2));
$OpTx$FX_DC$127 <= (NOT note_cnt(2) AND note_cnt(1) AND NOT note_cnt(3) AND
      NOT note_cnt(4) AND NOT note_cnt(0));
AUDIO(0) <= NOT (AUDIO(1)
      XOR
     AUDIO(0) <= NOT (((AUDIO(3) AND sine_tbl_ind(0))
      OR (NOT AUDIO(3) AND NOT sine_tbl_ind(0))));
FDCPE_AUDIO1: FDCPE port map (AUDIO(1),AUDIO_D(1),CLK_FAST,'0','0');
     AUDIO_D(1) <= ((AUDIO(1) AND NOT rst AND NOT sine_cnt_en)
      OR (sine_tbl_ind(0) AND NOT rst AND sine_cnt_en AND
      NOT sine_tbl_ind_Maddsub__addsub0000_Mxor_Result(1)__xor0000/sine_tbl_ind_Maddsub__addsub0000_Mxor_Result(1)__xor0000_D)
      OR (NOT sine_tbl_ind(0) AND NOT rst AND sine_cnt_en AND
      sine_tbl_ind_Maddsub__addsub0000_Mxor_Result(1)__xor0000/sine_tbl_ind_Maddsub__addsub0000_Mxor_Result(1)__xor0000_D));
AUDIO(2) <= ((AUDIO(1) AND AUDIO(3))
      OR (AUDIO(1) AND sine_tbl_ind(0))
      OR (AUDIO(3) AND sine_tbl_ind(0)));
FTCPE_AUDIO3: FTCPE port map (AUDIO(3),AUDIO_T(3),CLK_FAST,'0','0');
     AUDIO_T(3) <= ((AUDIO(3) AND rst)
      OR (sine_tbl_ind(0) AND NOT rst AND sine_cnt_en AND NOT LED(1) AND
      sine_tbl_ind_Maddsub__addsub0000_Mxor_Result(1)__xor0000/sine_tbl_ind_Maddsub__addsub0000_Mxor_Result(1)__xor0000_D)
      OR (NOT sine_tbl_ind(0) AND NOT rst AND sine_cnt_en AND LED(1) AND
      sine_tbl_ind_Maddsub__addsub0000_Mxor_Result(1)__xor0000/sine_tbl_ind_Maddsub__addsub0000_Mxor_Result(1)__xor0000_D));
FDCPE_LED0: FDCPE port map (LED(0),LED_D(0),CLK_SLOW,'0','0');
     LED_D(0) <= ((LED(0) AND NOT song_ind_0__or0000/song_ind_0__or0000_D2)
      OR (NOT LED(0) AND NOT rst AND
      song_ind_0__or0000/song_ind_0__or0000_D2));
FTCPE_LED1: FTCPE port map (LED(1),LED_T(1),CLK_FAST,'0','0');
     LED_T(1) <= ((rst AND LED(1))
      OR (NOT AUDIO(1) AND NOT AUDIO(3) AND sine_tbl_ind(0) AND
      sine_cnt_en AND LED(1))
      OR (AUDIO(1) AND AUDIO(3) AND NOT sine_tbl_ind(0) AND NOT rst AND
      sine_cnt_en AND NOT LED(1)));
Madd_note_cnt_share0000__and0000/Madd_note_cnt_share0000__and0000_D2 <= (note_cnt(1) AND note_cnt(0));
Madd_note_cnt_share0000__and0003/Madd_note_cnt_share0000__and0003_D2 <= (note_cnt(2) AND note_cnt(3) AND note_cnt(4) AND
      Madd_note_cnt_share0000__and0000/Madd_note_cnt_share0000__and0000_D2);
Mrom_note_doA_or0002/Mrom_note_doA_or0002_D2 <= ((song_ind(2) AND NOT song_ind(3) AND NOT song_ind(4) AND
      NOT song_ind(5))
      OR (song_ind(2) AND NOT song_ind(3) AND NOT song_ind(5) AND
      NOT song_ind(1))
      OR (song_ind(2) AND NOT song_ind(4) AND NOT song_ind(5) AND
      NOT song_ind(1))
      OR (NOT song_ind(2) AND NOT song_ind(3) AND NOT song_ind(4) AND
      song_ind(5)));
N0/N0_D2 <= ((EXP6_.EXP)
      OR (song_delay(3).EXP)
      OR (NOT note_cnt(5) AND NOT note_cnt(4) AND note(0)/note(0)_D2)
      OR (NOT note_cnt(5) AND NOT note_cnt(4) AND NOT note(2)/note(2)_D2)
      OR (NOT note_cnt(5) AND NOT note_cnt(3) AND note(0)/note(0)_D2 AND
      note(2)/note(2)_D2)
      OR (NOT note(1)/note(1)_D2 AND note(0)/note(0)_D2 AND
      note(2)/note(2)_D2 AND NOT $OpTx$FX_DC$127)
      OR (NOT song_ind(3) AND NOT song_ind(4) AND NOT note_cnt(5) AND
      NOT note_cnt(4) AND note(1)/note(1)_D2));
N35/N35_D2 <= ((song_ind(3) AND song_ind(5))
      OR (NOT song_ind(2) AND song_ind(5) AND
      NOT Mrom_note_doA_or0002/Mrom_note_doA_or0002_D2)
      OR (song_ind(2) AND NOT song_ind(3) AND song_ind(4) AND
      NOT Mrom_note_doA_or0002/Mrom_note_doA_or0002_D2)
      OR (song_ind(2) AND NOT song_ind(4) AND song_ind(1) AND
      NOT Mrom_note_doA_or0002/Mrom_note_doA_or0002_D2));
note(0)/note(0)_D2 <= ((Mrom_note_doA_or0002/Mrom_note_doA_or0002_D2)
      OR (song_ind(2) AND NOT N35/N35_D2)
      OR (NOT LED(0) AND NOT song_ind(3) AND NOT song_ind(4) AND NOT N35/N35_D2));
note(1)/note(1)_D2 <= ((song_ind(2) AND song_ind(3) AND song_ind(4) AND
      NOT song_ind(5))
      OR (NOT song_ind(2) AND song_ind(3) AND NOT song_ind(4) AND
      NOT song_ind(5))
      OR (NOT song_ind(2) AND NOT song_ind(3) AND song_ind(4) AND
      NOT song_ind(5))
      OR (LED(0) AND NOT song_ind(2) AND NOT song_ind(4) AND
      NOT song_ind(5) AND NOT song_ind(1))
      OR (NOT LED(0) AND NOT song_ind(2) AND NOT song_ind(4) AND
      NOT song_ind(5) AND song_ind(1)));
note(2)/note(2)_D2 <= ((song_ind(2) AND
      NOT Mrom_note_doA_or0002/Mrom_note_doA_or0002_D2)
      OR (song_ind(5) AND
      NOT Mrom_note_doA_or0002/Mrom_note_doA_or0002_D2)
      OR (NOT song_ind(3) AND NOT song_ind(4) AND
      NOT song_ind_Madd__add0000__and0000/song_ind_Madd__add0000__and0000_D2 AND NOT Mrom_note_doA_or0002/Mrom_note_doA_or0002_D2));
FDCPE_note_cnt0: FDCPE port map (note_cnt(0),note_cnt_D(0),CLK_FAST,'0','0');
     note_cnt_D(0) <= ((NOT rst AND note_cnt(0) AND N35/N35_D2)
      OR (NOT rst AND NOT note_cnt(0) AND N0/N0_D2));
FDCPE_note_cnt1: FDCPE port map (note_cnt(1),note_cnt_D(1),CLK_FAST,'0','0');
     note_cnt_D(1) <= ((NOT rst AND note_cnt(1) AND N35/N35_D2)
      OR (NOT rst AND note_cnt(1) AND NOT note_cnt(0) AND N0/N0_D2)
      OR (NOT rst AND NOT note_cnt(1) AND note_cnt(0) AND N0/N0_D2));
FDCPE_note_cnt2: FDCPE port map (note_cnt(2),note_cnt_D(2),CLK_FAST,'0','0');
     note_cnt_D(2) <= ((NOT rst AND note_cnt(2) AND N35/N35_D2)
      OR (NOT rst AND note_cnt(2) AND N0/N0_D2 AND
      NOT Madd_note_cnt_share0000__and0000/Madd_note_cnt_share0000__and0000_D2)
      OR (NOT rst AND NOT note_cnt(2) AND N0/N0_D2 AND
      Madd_note_cnt_share0000__and0000/Madd_note_cnt_share0000__and0000_D2));
FDCPE_note_cnt3: FDCPE port map (note_cnt(3),note_cnt_D(3),CLK_FAST,'0','0');
     note_cnt_D(3) <= ((NOT rst AND note_cnt(3) AND N35/N35_D2)
      OR (NOT rst AND NOT note_cnt(2) AND note_cnt(3) AND N0/N0_D2)
      OR (NOT rst AND note_cnt(3) AND N0/N0_D2 AND
      NOT Madd_note_cnt_share0000__and0000/Madd_note_cnt_share0000__and0000_D2)
      OR (NOT rst AND note_cnt(2) AND NOT note_cnt(3) AND N0/N0_D2 AND
      Madd_note_cnt_share0000__and0000/Madd_note_cnt_share0000__and0000_D2));
FDCPE_note_cnt4: FDCPE port map (note_cnt(4),note_cnt_D(4),CLK_FAST,'0','0');
     note_cnt_D(4) <= ((NOT rst AND note_cnt(4) AND N35/N35_D2)
      OR (NOT rst AND note_cnt(4) AND N0/N0_D2 AND
      NOT Madd_note_cnt_share0000__and0003/Madd_note_cnt_share0000__and0003_D2)
      OR (NOT rst AND note_cnt(2) AND note_cnt(3) AND NOT note_cnt(4) AND
      N0/N0_D2 AND
      Madd_note_cnt_share0000__and0000/Madd_note_cnt_share0000__and0000_D2));
FDCPE_note_cnt5: FDCPE port map (note_cnt(5),note_cnt_D(5),CLK_FAST,'0','0');
     note_cnt_D(5) <= ((NOT rst AND note_cnt(5) AND N35/N35_D2)
      OR (NOT rst AND note_cnt(5) AND N0/N0_D2 AND
      NOT Madd_note_cnt_share0000__and0003/Madd_note_cnt_share0000__and0003_D2)
      OR (NOT rst AND NOT note_cnt(5) AND N0/N0_D2 AND
      Madd_note_cnt_share0000__and0003/Madd_note_cnt_share0000__and0003_D2));
FDCPE_rst: FDCPE port map (rst,NOT TASTER_RES,CLK_FAST,'0','0');
FDCPE_sine_cnt_en: FDCPE port map (sine_cnt_en,sine_cnt_en_D,CLK_FAST,'0','0');
     sine_cnt_en_D <= (NOT rst AND NOT note_cnt(2) AND NOT note_cnt(5) AND NOT note_cnt(1) AND
      NOT note_cnt(3) AND NOT note_cnt(4) AND NOT note_cnt(0) AND NOT $OpTx$FX_DC$111);
FDCPE_sine_tbl_ind0: FDCPE port map (sine_tbl_ind(0),sine_tbl_ind_D(0),CLK_FAST,'0','0');
     sine_tbl_ind_D(0) <= ((sine_tbl_ind(0) AND NOT rst AND NOT sine_cnt_en)
      OR (NOT sine_tbl_ind(0) AND NOT rst AND sine_cnt_en));
sine_tbl_ind_Maddsub__addsub0000_Mxor_Result(1)__xor0000/sine_tbl_ind_Maddsub__addsub0000_Mxor_Result(1)__xor0000_D <= LED(1)
      XOR
     sine_tbl_ind_Maddsub__addsub0000_Mxor_Result(1)__xor0000/sine_tbl_ind_Maddsub__addsub0000_Mxor_Result(1)__xor0000_D <= AUDIO(1);
FDCPE_song_delay0: FDCPE port map (song_delay(0),song_delay_D(0),CLK_SLOW,'0','0');
     song_delay_D(0) <= (NOT song_delay(0) AND
      NOT song_delay_or0000/song_delay_or0000_D2);
FDCPE_song_delay1: FDCPE port map (song_delay(1),song_delay_D(1),CLK_SLOW,'0','0');
     song_delay_D(1) <= ((song_delay(0) AND NOT song_delay(1) AND
      NOT song_delay_or0000/song_delay_or0000_D2)
      OR (NOT song_delay(0) AND song_delay(1) AND
      NOT song_delay_or0000/song_delay_or0000_D2));
FDCPE_song_delay2: FDCPE port map (song_delay(2),song_delay_D(2),CLK_SLOW,'0','0');
     song_delay_D(2) <= ((song_delay(2) AND
      NOT song_delay_or0000/song_delay_or0000_D2 AND
      NOT song_delay_Madd__add0000__and0001/song_delay_Madd__add0000__and0001_D2)
      OR (song_delay(0) AND song_delay(1) AND
      NOT song_delay_or0000/song_delay_or0000_D2 AND
      NOT song_delay_Madd__add0000__and0001/song_delay_Madd__add0000__and0001_D2));
FDCPE_song_delay3: FDCPE port map (song_delay(3),song_delay(4).EXP,CLK_SLOW,'0','0');
FTCPE_song_delay4: FTCPE port map (song_delay(4),song_delay_T(4),CLK_SLOW,'0','0');
     song_delay_T(4) <= ((song_delay(4) AND
      song_delay_or0000/song_delay_or0000_D2)
      OR (song_delay(3) AND
      NOT song_delay_or0000/song_delay_or0000_D2 AND
      song_delay_Madd__add0000__and0001/song_delay_Madd__add0000__and0001_D2));
FDCPE_song_delay5: FDCPE port map (song_delay(5),song_delay_D(5),CLK_SLOW,'0','0');
     song_delay_D(5) <= ((song_delay(5) AND
      NOT song_delay_or0000/song_delay_or0000_D2 AND
      NOT song_delay_Madd__add0000__and0004/song_delay_Madd__add0000__and0004_D2)
      OR (song_delay(3) AND song_delay(4) AND
      NOT song_delay_or0000/song_delay_or0000_D2 AND
      song_delay_Madd__add0000__and0001/song_delay_Madd__add0000__and0001_D2 AND
      NOT song_delay_Madd__add0000__and0004/song_delay_Madd__add0000__and0004_D2));
FDCPE_song_delay6: FDCPE port map (song_delay(6),song_delay_D(6),CLK_SLOW,'0','0');
     song_delay_D(6) <= ((song_delay(6) AND
      NOT song_delay_or0000/song_delay_or0000_D2 AND
      NOT song_delay_Madd__add0000__and0004/song_delay_Madd__add0000__and0004_D2)
      OR (NOT song_delay(6) AND
      NOT song_delay_or0000/song_delay_or0000_D2 AND
      song_delay_Madd__add0000__and0004/song_delay_Madd__add0000__and0004_D2));
song_delay_Madd__add0000__and0001/song_delay_Madd__add0000__and0001_D2 <= (song_delay(0) AND song_delay(1) AND song_delay(2));
song_delay_Madd__add0000__and0004/song_delay_Madd__add0000__and0004_D2 <= (song_delay(3) AND song_delay(4) AND song_delay(5) AND
      song_delay_Madd__add0000__and0001/song_delay_Madd__add0000__and0001_D2);
song_delay_or0000/song_delay_or0000_D2 <= ((rst)
      OR (NOT song_delay(0) AND song_delay(1) AND song_delay(2) AND
      song_delay(3) AND NOT song_delay(4) AND song_delay(5) AND song_delay(6)));
FTCPE_song_ind1: FTCPE port map (song_ind(1),song_ind_T(1),CLK_SLOW,'0','0');
     song_ind_T(1) <= ((LED(0) AND song_ind_0__or0000/song_ind_0__or0000_D2 AND
      NOT song_ind_or0000/song_ind_or0000_D2)
      OR (song_ind(1) AND
      song_ind_0__or0000/song_ind_0__or0000_D2 AND song_ind_or0000/song_ind_or0000_D2));
FTCPE_song_ind2: FTCPE port map (song_ind(2),song_ind_T(2),CLK_SLOW,'0','0');
     song_ind_T(2) <= ((song_ind(2) AND
      song_ind_0__or0000/song_ind_0__or0000_D2 AND song_ind_or0000/song_ind_or0000_D2)
      OR (song_ind_0__or0000/song_ind_0__or0000_D2 AND
      NOT song_ind_or0000/song_ind_or0000_D2 AND
      song_ind_Madd__add0000__and0000/song_ind_Madd__add0000__and0000_D2));
FTCPE_song_ind3: FTCPE port map (song_ind(3),song_ind_T(3),CLK_SLOW,'0','0');
     song_ind_T(3) <= ((song_ind(3) AND
      song_ind_0__or0000/song_ind_0__or0000_D2 AND song_ind_or0000/song_ind_or0000_D2)
      OR (song_ind(2) AND
      song_ind_0__or0000/song_ind_0__or0000_D2 AND NOT song_ind_or0000/song_ind_or0000_D2 AND
      song_ind_Madd__add0000__and0000/song_ind_Madd__add0000__and0000_D2));
FDCPE_song_ind4: FDCPE port map (song_ind(4),song_ind_D(4),CLK_SLOW,'0','0');
     song_ind_D(4) <= ((song_ind(4) AND NOT $OpTx$FX_DC$116)
      OR (song_ind(2) AND song_ind(3) AND NOT song_ind(4) AND
      song_ind_0__or0000/song_ind_0__or0000_D2 AND NOT song_ind_or0000/song_ind_or0000_D2 AND
      song_ind_Madd__add0000__and0000/song_ind_Madd__add0000__and0000_D2));
FDCPE_song_ind5: FDCPE port map (song_ind(5),song_ind_D(5),CLK_SLOW,'0','0');
     song_ind_D(5) <= ((song_ind(5) AND NOT $OpTx$FX_DC$116)
      OR (song_ind(2) AND song_ind(3) AND song_ind(4) AND
      NOT song_ind(5) AND song_ind_0__or0000/song_ind_0__or0000_D2 AND
      NOT song_ind_or0000/song_ind_or0000_D2 AND
      song_ind_Madd__add0000__and0000/song_ind_Madd__add0000__and0000_D2));
song_ind_0__or0000/song_ind_0__or0000_D2 <= ((rst)
      OR (NOT song_delay(0) AND NOT song_delay(1) AND NOT song_delay(2) AND
      NOT song_delay(3) AND NOT song_delay(4) AND NOT song_delay(5) AND NOT song_delay(6)));
song_ind_Madd__add0000__and0000/song_ind_Madd__add0000__and0000_D2 <= (LED(0) AND song_ind(1));
song_ind_or0000/song_ind_or0000_D2 <= ((rst)
      OR (song_ind(2) AND NOT song_ind(3) AND NOT song_ind(4) AND
      song_ind(5) AND song_ind_0__or0000/song_ind_0__or0000_D2 AND
      song_ind_Madd__add0000__and0000/song_ind_Madd__add0000__and0000_D2));
Register Legend:
      FDCPE (Q,D,C,CLR,PRE,CE);
      FTCPE (Q,D,C,CLR,PRE,CE);
      LDCP (Q,D,G,CLR,PRE);