cpldfit:  version K.39                              Xilinx Inc.
                                  Fitter Report
Design Name: main                                Date:  4- 4-2009,  6:55PM
Device Used: XC9572XL-10-PC44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
36 /72  ( 50%) 84  /360  ( 23%) 42 /216 ( 19%)   26 /72  ( 36%) 16 /34  ( 47%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1           4/18        6/54        8/90       5/ 9
FB2          18/18*      22/54       40/90       4/ 9
FB3           0/18        0/54        0/90       0/ 9
FB4          14/18       14/54       36/90       7/ 7*
             -----       -----       -----      -----    
             36/72       42/216      84/360     16/34 

* - Resource is exhausted

** Global Control Resources **

Signal 'CLK_FAST' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    1           1    |  I/O              :    15      28
Output        :   14          14    |  GCK/IO           :     1       3
Bidirectional :    0           0    |  GTS/IO           :     0       2
GCK           :    1           1    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     16          16

** Power Data **

There are 0 macrocells in high performance mode (MCHP).
There are 36 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 14 Outputs **

Signal                    Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                      Pts   Inps          No.  Type    Use     Mode Rate State
LED<0>                    2     4     FB1_2   1~   I/O     O       LOW  SLOW RESET
LED<1>                    2     4     FB1_5   2~   I/O     O       LOW  SLOW RESET
LED<2>                    2     4     FB1_6   3~   I/O     O       LOW  SLOW RESET
LED<3>                    2     4     FB1_8   4~   I/O     O       LOW  SLOW RESET
DP                        0     0     FB2_2   35~  I/O     O       LOW  SLOW 
EN_DISP<0>                2     20    FB2_5   36~  I/O     O       LOW  FAST RESET
EN_DISP<1>                3     21    FB2_6   37~  I/O     O       LOW  FAST SET
G                         2     4     FB4_2   25~  I/O     O       LOW  SLOW 
D                         4     7     FB4_5   26~  I/O     O       LOW  SLOW 
C                         3     4     FB4_8   27~  I/O     O       LOW  SLOW 
F                         4     5     FB4_11  28~  I/O     O       LOW  SLOW 
E                         3     4     FB4_14  29~  I/O     O       LOW  SLOW 
B                         5     5     FB4_15  33~  I/O     O       LOW  SLOW 
A                         3     6     FB4_17  34~  I/O     O       LOW  SLOW 

** 22 Buried Nodes **

Signal                    Total Total Loc     Pwr  Reg Init
Name                      Pts   Inps          Mode State
cnt_low0/cnt_low0_CE      1     16    FB2_1   LOW  
cnt_low0                  1     16    FB2_3   LOW  RESET
cnt_low3                  2     18    FB2_4   LOW  RESET
cnt_low2                  2     17    FB2_7   LOW  RESET
cnt_low1                  2     17    FB2_8   LOW  RESET
XLXI_18/Q<0>              2     9     FB2_9   LOW  RESET
XLXI_16/Q<7>              2     8     FB2_10  LOW  RESET
XLXI_16/Q<6>              2     7     FB2_11  LOW  RESET
XLXI_18/Q<7>              3     16    FB2_12  LOW  RESET
XLXI_18/Q<6>              3     15    FB2_13  LOW  RESET
XLXI_18/Q<5>              3     14    FB2_14  LOW  RESET
XLXI_18/Q<4>              3     13    FB2_15  LOW  RESET
XLXI_18/Q<3>              3     12    FB2_16  LOW  RESET
XLXI_18/Q<2>              3     11    FB2_17  LOW  RESET
XLXI_18/Q<1>              3     10    FB2_18  LOW  RESET
XLXI_38/T2/XLXI_38/T2_D2  1     2     FB4_7   LOW  
XLXI_16/Q<0>              1     1     FB4_9   LOW  RESET
XLXI_16/Q<5>              2     6     FB4_10  LOW  RESET
XLXI_16/Q<4>              2     5     FB4_12  LOW  RESET
XLXI_16/Q<3>              2     4     FB4_13  LOW  RESET
XLXI_16/Q<2>              2     3     FB4_16  LOW  RESET
XLXI_16/Q<1>              2     2     FB4_18  LOW  RESET

** 2 Inputs **

Signal                    Loc     Pin  Pin     Pin     
Name                              No.  Type    Use     
CLK_FAST                  FB1_9   5~   GCK/I/O GCK
TASTER_RES                FB2_8   38~  I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               6/48
Number of signals used by logic mapping into function block:  6
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1         (b)     
LED<0>                2       0     0   3     FB1_2   1~    I/O     O
(unused)              0       0     0   5     FB1_3         (b)     
(unused)              0       0     0   5     FB1_4         (b)     
LED<1>                2       0     0   3     FB1_5   2~    I/O     O
LED<2>                2       0     0   3     FB1_6   3~    I/O     O
(unused)              0       0     0   5     FB1_7         (b)     
LED<3>                2       0     0   3     FB1_8   4~    I/O     O
(unused)              0       0     0   5     FB1_9   5     GCK/I/O GCK
(unused)              0       0     0   5     FB1_10        (b)     
(unused)              0       0     0   5     FB1_11  6     GCK/I/O 
(unused)              0       0     0   5     FB1_12        (b)     
(unused)              0       0     0   5     FB1_13        (b)     
(unused)              0       0     0   5     FB1_14  7     GCK/I/O 
(unused)              0       0     0   5     FB1_15  8     I/O     
(unused)              0       0     0   5     FB1_16        (b)     
(unused)              0       0     0   5     FB1_17  9     I/O     
(unused)              0       0     0   5     FB1_18        (b)     

Signals Used by Logic in Function Block
  1: LED<0>             3: LED<2>             5: TASTER_RES 
  2: LED<1>             4: LED<3>             6: cnt_low0/cnt_low0_CE 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
LED<0>               X..XXX.................................. 4
LED<1>               XX..XX.................................. 4
LED<2>               .XX.XX.................................. 4
LED<3>               ..XXXX.................................. 4
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               22/32
Number of signals used by logic mapping into function block:  22
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
cnt_low0/cnt_low0_CE
                      1       0     0   4     FB2_1         (b)     (b)
DP                    0       0     0   5     FB2_2   35~   I/O     O
cnt_low0              1       0     0   4     FB2_3         (b)     (b)
cnt_low3              2       0     0   3     FB2_4         (b)     (b)
EN_DISP<0>            2       0     0   3     FB2_5   36~   I/O     O
EN_DISP<1>            3       0     0   2     FB2_6   37~   I/O     O
cnt_low2              2       0     0   3     FB2_7         (b)     (b)
cnt_low1              2       0     0   3     FB2_8   38    I/O     I
XLXI_18/Q<0>          2       0     0   3     FB2_9   39    GSR/I/O (b)
XLXI_16/Q<7>          2       0     0   3     FB2_10        (b)     (b)
XLXI_16/Q<6>          2       0     0   3     FB2_11  40    GTS/I/O (b)
XLXI_18/Q<7>          3       0     0   2     FB2_12        (b)     (b)
XLXI_18/Q<6>          3       0     0   2     FB2_13        (b)     (b)
XLXI_18/Q<5>          3       0     0   2     FB2_14  42    GTS/I/O (b)
XLXI_18/Q<4>          3       0     0   2     FB2_15  43    I/O     (b)
XLXI_18/Q<3>          3       0     0   2     FB2_16        (b)     (b)
XLXI_18/Q<2>          3       0     0   2     FB2_17  44    I/O     (b)
XLXI_18/Q<1>          3       0     0   2     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: EN_DISP<0>         9: XLXI_16/Q<6>      16: XLXI_18/Q<5> 
  2: TASTER_RES        10: XLXI_16/Q<7>      17: XLXI_18/Q<6> 
  3: XLXI_16/Q<0>      11: XLXI_18/Q<0>      18: XLXI_18/Q<7> 
  4: XLXI_16/Q<1>      12: XLXI_18/Q<1>      19: XLXI_38/T2/XLXI_38/T2_D2 
  5: XLXI_16/Q<2>      13: XLXI_18/Q<2>      20: cnt_low0 
  6: XLXI_16/Q<3>      14: XLXI_18/Q<3>      21: cnt_low2 
  7: XLXI_16/Q<4>      15: XLXI_18/Q<4>      22: cnt_low3 
  8: XLXI_16/Q<5>     

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
cnt_low0/cnt_low0_CE 
                     ..XXXXXXXXXXXXXXXX...................... 16
DP                   ........................................ 0
cnt_low0             ..XXXXXXXXXXXXXXXX...................... 16
cnt_low3             ..XXXXXXXXXXXXXXXXX.X................... 18
EN_DISP<0>           .XXXXXXXXXXXXXXXXXX.XX.................. 20
EN_DISP<1>           XXXXXXXXXXXXXXXXXXX.XX.................. 21
cnt_low2             ..XXXXXXXXXXXXXXXXX..................... 17
cnt_low1             ..XXXXXXXXXXXXXXXX.X.................... 17
XLXI_18/Q<0>         .XXXXXXXXX.............................. 9
XLXI_16/Q<7>         .XXXXXXXX............................... 8
XLXI_16/Q<6>         .XXXXXXX................................ 7
XLXI_18/Q<7>         .XXXXXXXXXXXXXXXX....................... 16
XLXI_18/Q<6>         .XXXXXXXXXXXXXXX........................ 15
XLXI_18/Q<5>         .XXXXXXXXXXXXXX......................... 14
XLXI_18/Q<4>         .XXXXXXXXXXXXX.......................... 13
XLXI_18/Q<3>         .XXXXXXXXXXXX........................... 12
XLXI_18/Q<2>         .XXXXXXXXXXX............................ 11
XLXI_18/Q<1>         .XXXXXXXXXX............................. 10
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB3_1         (b)     
(unused)              0       0     0   5     FB3_2   11    I/O     
(unused)              0       0     0   5     FB3_3         (b)     
(unused)              0       0     0   5     FB3_4         (b)     
(unused)              0       0     0   5     FB3_5   12    I/O     
(unused)              0       0     0   5     FB3_6         (b)     
(unused)              0       0     0   5     FB3_7         (b)     
(unused)              0       0     0   5     FB3_8   13    I/O     
(unused)              0       0     0   5     FB3_9   14    I/O     
(unused)              0       0     0   5     FB3_10        (b)     
(unused)              0       0     0   5     FB3_11  18    I/O     
(unused)              0       0     0   5     FB3_12        (b)     
(unused)              0       0     0   5     FB3_13        (b)     
(unused)              0       0     0   5     FB3_14  19    I/O     
(unused)              0       0     0   5     FB3_15  20    I/O     
(unused)              0       0     0   5     FB3_16  24    I/O     
(unused)              0       0     0   5     FB3_17  22    I/O     
(unused)              0       0     0   5     FB3_18        (b)     
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               14/40
Number of signals used by logic mapping into function block:  14
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1         (b)     
G                     2       0     0   3     FB4_2   25~   I/O     O
(unused)              0       0     0   5     FB4_3         (b)     
(unused)              0       0     0   5     FB4_4         (b)     
D                     4       0     0   1     FB4_5   26~   I/O     O
(unused)              0       0     0   5     FB4_6         (b)     
XLXI_38/T2/XLXI_38/T2_D2
                      1       0     0   4     FB4_7         (b)     (b)
C                     3       0     0   2     FB4_8   27~   I/O     O
XLXI_16/Q<0>          1       0     0   4     FB4_9         (b)     (b)
XLXI_16/Q<5>          2       0     0   3     FB4_10        (b)     (b)
F                     4       0     0   1     FB4_11  28~   I/O     O
XLXI_16/Q<4>          2       0     0   3     FB4_12        (b)     (b)
XLXI_16/Q<3>          2       0     0   3     FB4_13        (b)     (b)
E                     3       0     0   2     FB4_14  29~   I/O     O
B                     5       0     0   0     FB4_15  33~   I/O     O
XLXI_16/Q<2>          2       0     0   3     FB4_16        (b)     (b)
A                     3       0     0   2     FB4_17  34~   I/O     O
XLXI_16/Q<1>          2       0     0   3     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: B                  6: XLXI_16/Q<1>              11: cnt_low0 
  2: E                  7: XLXI_16/Q<2>              12: cnt_low1 
  3: F                  8: XLXI_16/Q<3>              13: cnt_low2 
  4: TASTER_RES         9: XLXI_16/Q<4>              14: cnt_low3 
  5: XLXI_16/Q<0>      10: XLXI_38/T2/XLXI_38/T2_D2 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
G                    .........X.XXX.......................... 4
D                    XX.......XXXXX.......................... 7
XLXI_38/T2/XLXI_38/T2_D2 
                     ..........XX............................ 2
C                    ..........XXXX.......................... 4
XLXI_16/Q<0>         ...X.................................... 1
XLXI_16/Q<5>         ...XXXXXX............................... 6
F                    .X.......X.XXX.......................... 5
XLXI_16/Q<4>         ...XXXXX................................ 5
XLXI_16/Q<3>         ...XXXX................................. 4
E                    ..........XXXX.......................... 4
B                    ..X.......XXXX.......................... 5
XLXI_16/Q<2>         ...XXX.................................. 3
A                    XX.......X.XXX.......................... 6
XLXI_16/Q<1>         ...XX................................... 2
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********


A <= ((NOT cnt_low2 AND B)
	OR (NOT cnt_low1 AND cnt_low2 AND NOT E)
	OR (NOT cnt_low3 AND NOT B AND E AND NOT XLXI_38/T2/XLXI_38/T2_D2));


B <= ((cnt_low1 AND cnt_low0 AND NOT F)
	OR (cnt_low1 AND cnt_low3 AND cnt_low2)
	OR (cnt_low1 AND NOT cnt_low3 AND NOT F)
	OR (cnt_low0 AND NOT cnt_low3 AND NOT F)
	OR (NOT cnt_low0 AND cnt_low3 AND cnt_low2));


C <= ((cnt_low1 AND cnt_low3 AND cnt_low2)
	OR (NOT cnt_low0 AND cnt_low3 AND cnt_low2)
	OR (cnt_low1 AND NOT cnt_low0 AND NOT cnt_low3 AND NOT cnt_low2));


D <= ((cnt_low2 AND XLXI_38/T2/XLXI_38/T2_D2)
	OR (NOT cnt_low2 AND B AND E)
	OR (cnt_low1 AND NOT cnt_low0 AND cnt_low3 AND NOT cnt_low2)
	OR (NOT cnt_low3 AND NOT B AND E AND NOT XLXI_38/T2/XLXI_38/T2_D2));


DP <= '0';


E <= ((cnt_low1 AND cnt_low0 AND NOT cnt_low3)
	OR (NOT cnt_low1 AND cnt_low0 AND NOT cnt_low2)
	OR (NOT cnt_low1 AND NOT cnt_low3 AND cnt_low2));

FTCPE_EN_DISP0: FTCPE port map (EN_DISP(0),EN_DISP_T(0),CLK_FAST,NOT TASTER_RES,'0');
EN_DISP_T(0) <= (XLXI_18/Q(0) AND XLXI_18/Q(4) AND XLXI_18/Q(1) AND 
	XLXI_18/Q(5) AND XLXI_18/Q(2) AND XLXI_18/Q(6) AND XLXI_18/Q(3) AND 
	XLXI_18/Q(7) AND cnt_low3 AND cnt_low2 AND XLXI_16/Q(0) AND 
	XLXI_16/Q(4) AND XLXI_16/Q(1) AND XLXI_16/Q(5) AND XLXI_16/Q(2) AND 
	XLXI_16/Q(6) AND XLXI_16/Q(3) AND XLXI_16/Q(7) AND 
	XLXI_38/T2/XLXI_38/T2_D2);

FDCPE_EN_DISP1: FDCPE port map (EN_DISP(1),EN_DISP_D(1),CLK_FAST,'0',NOT TASTER_RES);
EN_DISP_D(1) <= EN_DISP(0)
	 XOR 
EN_DISP_D(1) <= (XLXI_18/Q(0) AND XLXI_18/Q(4) AND XLXI_18/Q(1) AND 
	XLXI_18/Q(5) AND XLXI_18/Q(2) AND XLXI_18/Q(6) AND XLXI_18/Q(3) AND 
	XLXI_18/Q(7) AND cnt_low3 AND cnt_low2 AND XLXI_16/Q(0) AND 
	XLXI_16/Q(4) AND XLXI_16/Q(1) AND XLXI_16/Q(5) AND XLXI_16/Q(2) AND 
	XLXI_16/Q(6) AND XLXI_16/Q(3) AND XLXI_16/Q(7) AND 
	XLXI_38/T2/XLXI_38/T2_D2);


F <= ((cnt_low1 AND NOT cnt_low3 AND NOT cnt_low2)
	OR (NOT cnt_low1 AND cnt_low2 AND NOT E)
	OR (NOT cnt_low3 AND NOT cnt_low2 AND E)
	OR (NOT cnt_low3 AND E AND XLXI_38/T2/XLXI_38/T2_D2));


G <= ((NOT cnt_low1 AND NOT cnt_low3 AND NOT cnt_low2)
	OR (NOT cnt_low3 AND cnt_low2 AND XLXI_38/T2/XLXI_38/T2_D2));

FDCPE_LED0: FDCPE port map (LED(0),LED_D(0),CLK_FAST,'0','0');
LED_D(0) <= ((TASTER_RES AND NOT LED(0) AND NOT cnt_low0/cnt_low0_CE)
	OR (TASTER_RES AND NOT LED(3) AND cnt_low0/cnt_low0_CE));

FDCPE_LED1: FDCPE port map (LED(1),LED_D(1),CLK_FAST,'0','0');
LED_D(1) <= ((TASTER_RES AND NOT LED(0) AND cnt_low0/cnt_low0_CE)
	OR (TASTER_RES AND NOT LED(1) AND NOT cnt_low0/cnt_low0_CE));

FDCPE_LED2: FDCPE port map (LED(2),LED_D(2),CLK_FAST,'0','0');
LED_D(2) <= ((TASTER_RES AND NOT LED(1) AND cnt_low0/cnt_low0_CE)
	OR (TASTER_RES AND NOT LED(2) AND NOT cnt_low0/cnt_low0_CE));

FDCPE_LED3: FDCPE port map (LED(3),LED_D(3),CLK_FAST,'0','0');
LED_D(3) <= ((TASTER_RES AND LED(2) AND cnt_low0/cnt_low0_CE)
	OR (TASTER_RES AND LED(3) AND NOT cnt_low0/cnt_low0_CE));

FTCPE_XLXI_16/Q0: FTCPE port map (XLXI_16/Q(0),'1',CLK_FAST,NOT TASTER_RES,'0');

FTCPE_XLXI_16/Q1: FTCPE port map (XLXI_16/Q(1),XLXI_16/Q(0),CLK_FAST,NOT TASTER_RES,'0');

FTCPE_XLXI_16/Q2: FTCPE port map (XLXI_16/Q(2),XLXI_16/Q_T(2),CLK_FAST,NOT TASTER_RES,'0');
XLXI_16/Q_T(2) <= (XLXI_16/Q(0) AND XLXI_16/Q(1));

FTCPE_XLXI_16/Q3: FTCPE port map (XLXI_16/Q(3),XLXI_16/Q_T(3),CLK_FAST,NOT TASTER_RES,'0');
XLXI_16/Q_T(3) <= (XLXI_16/Q(0) AND XLXI_16/Q(1) AND XLXI_16/Q(2));

FTCPE_XLXI_16/Q4: FTCPE port map (XLXI_16/Q(4),XLXI_16/Q_T(4),CLK_FAST,NOT TASTER_RES,'0');
XLXI_16/Q_T(4) <= (XLXI_16/Q(0) AND XLXI_16/Q(1) AND XLXI_16/Q(2) AND 
	XLXI_16/Q(3));

FTCPE_XLXI_16/Q5: FTCPE port map (XLXI_16/Q(5),XLXI_16/Q_T(5),CLK_FAST,NOT TASTER_RES,'0');
XLXI_16/Q_T(5) <= (XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND 
	XLXI_16/Q(2) AND XLXI_16/Q(3));

FTCPE_XLXI_16/Q6: FTCPE port map (XLXI_16/Q(6),XLXI_16/Q_T(6),CLK_FAST,NOT TASTER_RES,'0');
XLXI_16/Q_T(6) <= (XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND 
	XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(3));

FTCPE_XLXI_16/Q7: FTCPE port map (XLXI_16/Q(7),XLXI_16/Q_T(7),CLK_FAST,NOT TASTER_RES,'0');
XLXI_16/Q_T(7) <= (XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND 
	XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3));

FTCPE_XLXI_18/Q0: FTCPE port map (XLXI_18/Q(0),'1',CLK_FAST,NOT TASTER_RES,'0',XLXI_18/Q_CE(0));
XLXI_18/Q_CE(0) <= (XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND 
	XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND 
	XLXI_16/Q(7));

FTCPE_XLXI_18/Q1: FTCPE port map (XLXI_18/Q(1),XLXI_18/Q(0),CLK_FAST,NOT TASTER_RES,'0',XLXI_18/Q_CE(1));
XLXI_18/Q_CE(1) <= (XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND 
	XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND 
	XLXI_16/Q(7));

FTCPE_XLXI_18/Q2: FTCPE port map (XLXI_18/Q(2),XLXI_18/Q_T(2),CLK_FAST,NOT TASTER_RES,'0',XLXI_18/Q_CE(2));
XLXI_18/Q_T(2) <= (XLXI_18/Q(0) AND XLXI_18/Q(1));
XLXI_18/Q_CE(2) <= (XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND 
	XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND 
	XLXI_16/Q(7));

FTCPE_XLXI_18/Q3: FTCPE port map (XLXI_18/Q(3),XLXI_18/Q_T(3),CLK_FAST,NOT TASTER_RES,'0',XLXI_18/Q_CE(3));
XLXI_18/Q_T(3) <= (XLXI_18/Q(0) AND XLXI_18/Q(1) AND XLXI_18/Q(2));
XLXI_18/Q_CE(3) <= (XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND 
	XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND 
	XLXI_16/Q(7));

FTCPE_XLXI_18/Q4: FTCPE port map (XLXI_18/Q(4),XLXI_18/Q_T(4),CLK_FAST,NOT TASTER_RES,'0',XLXI_18/Q_CE(4));
XLXI_18/Q_T(4) <= (XLXI_18/Q(0) AND XLXI_18/Q(1) AND XLXI_18/Q(2) AND 
	XLXI_18/Q(3));
XLXI_18/Q_CE(4) <= (XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND 
	XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND 
	XLXI_16/Q(7));

FTCPE_XLXI_18/Q5: FTCPE port map (XLXI_18/Q(5),XLXI_18/Q_T(5),CLK_FAST,NOT TASTER_RES,'0',XLXI_18/Q_CE(5));
XLXI_18/Q_T(5) <= (XLXI_18/Q(0) AND XLXI_18/Q(4) AND XLXI_18/Q(1) AND 
	XLXI_18/Q(2) AND XLXI_18/Q(3));
XLXI_18/Q_CE(5) <= (XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND 
	XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND 
	XLXI_16/Q(7));

FTCPE_XLXI_18/Q6: FTCPE port map (XLXI_18/Q(6),XLXI_18/Q_T(6),CLK_FAST,NOT TASTER_RES,'0',XLXI_18/Q_CE(6));
XLXI_18/Q_T(6) <= (XLXI_18/Q(0) AND XLXI_18/Q(4) AND XLXI_18/Q(1) AND 
	XLXI_18/Q(5) AND XLXI_18/Q(2) AND XLXI_18/Q(3));
XLXI_18/Q_CE(6) <= (XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND 
	XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND 
	XLXI_16/Q(7));

FTCPE_XLXI_18/Q7: FTCPE port map (XLXI_18/Q(7),XLXI_18/Q_T(7),CLK_FAST,NOT TASTER_RES,'0',XLXI_18/Q_CE(7));
XLXI_18/Q_T(7) <= (XLXI_18/Q(0) AND XLXI_18/Q(4) AND XLXI_18/Q(1) AND 
	XLXI_18/Q(5) AND XLXI_18/Q(2) AND XLXI_18/Q(6) AND XLXI_18/Q(3));
XLXI_18/Q_CE(7) <= (XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND 
	XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND 
	XLXI_16/Q(7));


XLXI_38/T2/XLXI_38/T2_D2 <= (cnt_low1 AND cnt_low0);

FTCPE_cnt_low0: FTCPE port map (cnt_low0,'1',CLK_FAST,'0','0',cnt_low0_CE);
cnt_low0_CE <= (XLXI_18/Q(0) AND XLXI_18/Q(4) AND XLXI_18/Q(1) AND 
	XLXI_18/Q(5) AND XLXI_18/Q(2) AND XLXI_18/Q(6) AND XLXI_18/Q(3) AND 
	XLXI_18/Q(7) AND XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND 
	XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND 
	XLXI_16/Q(7));


cnt_low0/cnt_low0_CE <= (XLXI_18/Q(0) AND XLXI_18/Q(4) AND XLXI_18/Q(1) AND 
	XLXI_18/Q(5) AND XLXI_18/Q(2) AND XLXI_18/Q(6) AND XLXI_18/Q(3) AND 
	XLXI_18/Q(7) AND XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND 
	XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND 
	XLXI_16/Q(7));

FTCPE_cnt_low1: FTCPE port map (cnt_low1,cnt_low0,CLK_FAST,'0','0',cnt_low1_CE);
cnt_low1_CE <= (XLXI_18/Q(0) AND XLXI_18/Q(4) AND XLXI_18/Q(1) AND 
	XLXI_18/Q(5) AND XLXI_18/Q(2) AND XLXI_18/Q(6) AND XLXI_18/Q(3) AND 
	XLXI_18/Q(7) AND XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND 
	XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND 
	XLXI_16/Q(7));

FTCPE_cnt_low2: FTCPE port map (cnt_low2,XLXI_38/T2/XLXI_38/T2_D2,CLK_FAST,'0','0',cnt_low2_CE);
cnt_low2_CE <= (XLXI_18/Q(0) AND XLXI_18/Q(4) AND XLXI_18/Q(1) AND 
	XLXI_18/Q(5) AND XLXI_18/Q(2) AND XLXI_18/Q(6) AND XLXI_18/Q(3) AND 
	XLXI_18/Q(7) AND XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND 
	XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND 
	XLXI_16/Q(7));

FTCPE_cnt_low3: FTCPE port map (cnt_low3,cnt_low3_T,CLK_FAST,'0','0',cnt_low3_CE);
cnt_low3_T <= (cnt_low2 AND XLXI_38/T2/XLXI_38/T2_D2);
cnt_low3_CE <= (XLXI_18/Q(0) AND XLXI_18/Q(4) AND XLXI_18/Q(1) AND 
	XLXI_18/Q(5) AND XLXI_18/Q(2) AND XLXI_18/Q(6) AND XLXI_18/Q(3) AND 
	XLXI_18/Q(7) AND XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND 
	XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND 
	XLXI_16/Q(7));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9572XL-10-PC44


   --------------------------------  
  /6  5  4  3  2  1  44 43 42 41 40 \
 | 7                             39 | 
 | 8                             38 | 
 | 9                             37 | 
 | 10                            36 | 
 | 11       XC9572XL-10-PC44     35 | 
 | 12                            34 | 
 | 13                            33 | 
 | 14                            32 | 
 | 15                            31 | 
 | 16                            30 | 
 | 17                            29 | 
 \ 18 19 20 21 22 23 24 25 26 27 28 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 LED<0>                           23 GND                           
  2 LED<1>                           24 TIE                           
  3 LED<2>                           25 G                             
  4 LED<3>                           26 D                             
  5 CLK_FAST                         27 C                             
  6 TIE                              28 F                             
  7 TIE                              29 E                             
  8 TIE                              30 TDO                           
  9 TIE                              31 GND                           
 10 GND                              32 VCC                           
 11 TIE                              33 B                             
 12 TIE                              34 A                             
 13 TIE                              35 DP                            
 14 TIE                              36 EN_DISP<0>                    
 15 TDI                              37 EN_DISP<1>                    
 16 TMS                              38 TASTER_RES                    
 17 TCK                              39 TIE                           
 18 TIE                              40 TIE                           
 19 TIE                              41 VCC                           
 20 TIE                              42 TIE                           
 21 VCC                              43 TIE                           
 22 TIE                              44 TIE                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         KPR  = Unused I/O with weak keeper (leave unconnected)
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572xl-10-PC44
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : LOW
Ground on Unused IOs                        : OFF
Set I/O Pin Termination                     : FLOAT
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 25