Equations

********** Mapped Logic **********
A <= ((EXP13_.EXP)
      OR (EN_DISP(0) AND DIP(4) AND DIP(5) AND NOT DIP(6))
      OR (EN_DISP(0) AND DIP(5) AND NOT DIP(6) AND NOT DIP(7))
      OR (NOT EN_DISP(0) AND DIP(0) AND DIP(1) AND NOT DIP(2))
      OR (NOT EN_DISP(0) AND DIP(1) AND NOT DIP(2) AND NOT DIP(3))
      OR (NOT EN_DISP(0) AND NOT DIP(0) AND DIP(1) AND DIP(2) AND DIP(3)));
FTCPE_AUDIO0: FTCPE port map (AUDIO(0),'1',CLK_MID,NOT TASTER_RES,'0');
FTCPE_AUDIO1: FTCPE port map (AUDIO(1),AUDIO(0),CLK_MID,NOT TASTER_RES,'0');
FTCPE_AUDIO2: FTCPE port map (AUDIO(2),AUDIO_T(2),CLK_MID,NOT TASTER_RES,'0');
     AUDIO_T(2) <= (AUDIO(0) AND AUDIO(1));
FTCPE_AUDIO3: FTCPE port map (AUDIO(3),AUDIO_T(3),CLK_MID,NOT TASTER_RES,'0');
     AUDIO_T(3) <= (AUDIO(0) AND AUDIO(1) AND AUDIO(2));
B <= ((EXP12_.EXP)
      OR (EN_DISP(0) AND DIP(4) AND NOT DIP(6) AND NOT DIP(7))
      OR (EN_DISP(0) AND NOT DIP(4) AND NOT DIP(5) AND NOT DIP(7))
      OR (NOT EN_DISP(0) AND DIP(0) AND NOT DIP(1) AND NOT DIP(2))
      OR (NOT EN_DISP(0) AND DIP(0) AND NOT DIP(2) AND NOT DIP(3))
      OR (NOT EN_DISP(0) AND NOT DIP(0) AND NOT DIP(1) AND NOT DIP(3)));
C <= ((EXP8_.EXP)
      OR (EN_DISP(0) AND DIP(4) AND NOT DIP(6) AND NOT DIP(7))
      OR (EN_DISP(0) AND NOT DIP(5) AND NOT DIP(6) AND NOT DIP(7))
      OR (NOT EN_DISP(0) AND DIP(0) AND NOT DIP(2) AND NOT DIP(3))
      OR (NOT EN_DISP(0) AND NOT DIP(1) AND NOT DIP(2) AND NOT DIP(3))
      OR (NOT EN_DISP(0) AND DIP(0) AND NOT DIP(1) AND DIP(2) AND DIP(3)));
D <= ((EXP6_.EXP)
      OR (EXP7_.EXP)
      OR (EN_DISP(0) AND NOT DIP(4) AND NOT DIP(5) AND NOT DIP(6))
      OR (NOT EN_DISP(0) AND NOT DIP(0) AND NOT DIP(1) AND NOT DIP(2))
      OR (NOT EN_DISP(0) AND DIP(0) AND DIP(1) AND NOT DIP(2) AND DIP(3))
      OR (NOT EN_DISP(0) AND DIP(0) AND NOT DIP(1) AND DIP(2) AND NOT DIP(3))
      OR (NOT EN_DISP(0) AND NOT DIP(0) AND DIP(1) AND DIP(2) AND DIP(3)));
DP <= '0';
E <= ((EXP11_.EXP)
      OR (EN_DISP(0) AND NOT DIP(4) AND DIP(7))
      OR (NOT EN_DISP(0) AND NOT DIP(0) AND DIP(3))
      OR (EN_DISP(0) AND NOT DIP(4) AND DIP(5) AND DIP(6))
      OR (NOT EN_DISP(0) AND NOT DIP(0) AND DIP(1) AND DIP(2))
      OR (NOT EN_DISP(0) AND DIP(1) AND NOT DIP(2) AND DIP(3)));
FTCPE_EN_DISP0: FTCPE port map (EN_DISP(0),'1',CLK_MID,NOT TASTER_RES,'0');
FDCPE_EN_DISP1: FDCPE port map (EN_DISP(1),EN_DISP(0),CLK_MID,'0',NOT TASTER_RES);
F <= ((EXP9_.EXP)
      OR (EXP10_.EXP)
      OR (EN_DISP(0) AND DIP(5) AND NOT DIP(6) AND NOT DIP(7))
      OR (EN_DISP(0) AND NOT DIP(5) AND DIP(6) AND DIP(7))
      OR (NOT EN_DISP(0) AND NOT DIP(0) AND DIP(2) AND DIP(3))
      OR (NOT EN_DISP(0) AND DIP(1) AND NOT DIP(2) AND NOT DIP(3))
      OR (NOT EN_DISP(0) AND NOT DIP(1) AND DIP(2) AND DIP(3)));
G <= ((EN_DISP(0) AND DIP(5) AND DIP(6) AND DIP(7))
      OR (NOT EN_DISP(0) AND DIP(1) AND DIP(2) AND DIP(3))
      OR (EN_DISP(0) AND NOT DIP(4) AND NOT DIP(5) AND NOT DIP(6) AND DIP(7))
      OR (NOT EN_DISP(0) AND NOT DIP(0) AND NOT DIP(1) AND NOT DIP(2) AND DIP(3)));
LED(0) <= TASTER_U;
LED(1) <= TASTER_L;
LED(2) <= TASTER_R;
LED(3) <= TASTER_D;
Register Legend:
      FDCPE (Q,D,C,CLR,PRE,CE);
      FTCPE (Q,D,C,CLR,PRE,CE);
      LDCP (Q,D,G,CLR,PRE);